PURPOSE: To suppress an increase in cost, to improve the hit ratio of a hierarchical cash memory provided with a shadow directory and to make the cycle time of a high-speed computer, etc., including the hierarchical cash memory high speed and capable of high processing.

CONSTITUTION: In the hierarchical cache memory CM provided with a shadow directory SDR1, a dedicated shadow miss bit line SH is provided between the cache memories CM1 and CM2 of different hierarchies to transfer information on shadow miss bits S1 and S2 by way of the signal line. Thus, shadow miss information generated by the cache memory CM1 of a high-order hierarchy is transmitted to the memory CM2 of high-order and can be utilized for a replacing line selection processing at the time of miss-hitting of a main directory MDR2. The hit ratio of the cash memory CM can be improved without improviding the shadow directory for each cache memory of each hierarchy.