Title:
【発明の名称】メモリセル装置及びその製造方法
Document Type and Number:
Japanese Patent JP2002508594
Kind Code:
A
Abstract:
A method for fabricating a memory cell configuration, which includes the steps of etching isolation trenches into a semiconductor substrate and thereby forming webs between the isolation trenches and producing bit lines after channel regions have been produced. It furthermore includes performing an etching step which results in the isolation trenches penetrating more deeply into the semiconductor substrate.
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Inventors:
Reisinger, Hans
Application Number:
JP2000538387A
Publication Date:
March 19, 2002
Filing Date:
March 17, 1999
Export Citation:
Assignee:
Infineon Technologies AG
International Classes:
G11C17/08; H01L21/8246; H01L27/112; H01L27/115; H01L27/11568; (IPC1-7): H01L21/8246; H01L27/112; G11C17/08
Attorney, Agent or Firm:
Iwao Yamaguchi