PURPOSE: To speed up matching processing for TLBs between respective EPUs in the multiprocessor system.

CONSTITUTION: Copy TLBs 53a and 53b, and 63a and 63b of TLBs 11 and 21, and 31 and 41 in EPUs 1 and 2, and 3 and 4 are provided in SCUs 5a and 6a. When one of the EPUs 1, 2, 3, and 4 rewrites an address conversion table in a memory to erase ineffective address conversion pairs from the respective TLBs 1, 21, 31, and 41, the CTLBs 53a, 53b, 63a, and 63b are looked up with a logical address to be invalidated to detect the TLB wherein the address conversion pair to be invalidated is registered, and TLB invalidation processing is indicated to only the EPU having the TLB where the address conversion pair to be invalidated is registered to eliminate unnecessary TLB invalidation processing, thereby improving the performance of the system.