Title:
【発明の名称】多値ロジック変換装置
Document Type and Number:
Japanese Patent JPH0684983
Kind Code:
B2
Abstract:
PURPOSE:To obtain a converting circuit which is usable even when a LSI is increased in speed by compressing the conversion output obtained by converting a logic signal of an integer (n) larger than 2 into (n-1)-bit parallel data into prescribed bits, and converting the parallel data consisting of the prescribed bits into serial data with a prescribed clock and outputting the data. CONSTITUTION:A 1st block consists of a parallel data converter 1 which converts an (n)-valued logic signal In into (n-1)-bit parallel data and the 2nd block consists of a data compressor 2 which compresses (n-1)-bit data sent from the converter 1 into (k) bits. Here, the (n-1)-bit data is compressed into (k) bit (k: value obtained by rounding up the decimal of log2n) through hardware. A 3rd block parallel data from the compressor 2 into the serial data by using clock pulses corresponding to the (k) divisions of a state holding time and outputs it. Consequently, the use efficiency of a line is improved and the time division rate can be decreased.
Inventors:
TANAKA TAKAAKI
Application Number:
JP18210786A
Publication Date:
October 26, 1994
Filing Date:
August 01, 1986
Export Citation:
Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
G01R31/28; G01R31/317; G01R31/319; H03K19/20; G09G3/18; H03M9/00; H04N1/40; H04N1/405; (IPC1-7): G01R31/28; H03M9/00
Attorney, Agent or Firm:
Akira Kobiji (2 outside)