Title:
【発明の名称】高い垂直縦横比の多層薄膜構造
Document Type and Number:
Japanese Patent JP2001517155
Kind Code:
A
Abstract:
This invention relates to the area of microelectromechanical systems in which electronic circuits and mechanical devices are integrated on the same silicon chip. The method taught herein allows the fabrication of thin film structures in excess of 150 microns in height using thin film deposition processes. Wafers may be employed as reusable molds for efficient production of such structures. Various material properties may be varied within the structures to produce electrical, mechanical or electromechanical devices.
Inventors:
Keller Christopher Gee
Application Number:
JP50059097A
Publication Date:
October 02, 2001
Filing Date:
May 16, 1996
Export Citation:
Assignee:
The Regents of the University of California
International Classes:
A61K9/00; A61K9/50; B01D39/16; B81C1/00; B01D39/20; B01D67/00; B01D69/02; B01D69/12; B01D71/02; B44C1/22; B81B1/00; C03C15/00; C23C16/01; G03F7/00; H01L21/00; H01L21/302; H01L21/3065; H01L21/316; H01L29/84; H01L49/00; (IPC1-7): B81C1/00; H01L21/3065; H01L21/316
Attorney, Agent or Firm:
Minoru Nakamura (6 outside)