Title:
【発明の名称】マルチポートメモリ
Document Type and Number:
Japanese Patent JP2664843
Kind Code:
B2
Abstract:
A multiport memory comprises a pair of memory cells (21), at least a pair of bit line (BL, BL) and a pair of word lines (WL, WL) on a random access port side. One of the memory cell is connected to one bit line and one word line and the other memory cell is connected to the other bit line and the other word line. A pair of data lines (DQ, DQ) which are respectively connected to load elements (26, 27) are also provided in the random access port side of the multiport memory. A first switch circuit (24, 25) is connected between the pair of bit lines (BL, BL) and the pair of data lines (DQ, DQ). On a serial access port side, a data register (30) is connected between the pair of bit lines (BL, BL) to receive data transmitted through the pair of bit lines. A second switch circuit (28, 29) for transmitting data is connected between the pair of bit lines (BL, BL) and the data register (30). A control circuit (11, 12) opens the first switch circuit (24, 25), before closing the second switch circuit (28, 29) to transmit data stored in the memory cells to the data register.
Inventors:
Naoki Matsumoto
Tachio Igawa
Naruo Oshima
Tachio Igawa
Naruo Oshima
Application Number:
JP25262092A
Publication Date:
October 22, 1997
Filing Date:
September 22, 1992
Export Citation:
Assignee:
Toshiba Corporation
Toshiba Microelectronics Co., Ltd.
Toshiba Microelectronics Co., Ltd.
International Classes:
G11C11/401; G11C7/10; G11C11/4096; (IPC1-7): G11C11/401
Domestic Patent References:
| JP1119981A | ||||
| JP63261598A |
Attorney, Agent or Firm:
Takehiko Suzue