Title:
【発明の名称】マルチプロセッサ
Document Type and Number:
Japanese Patent JP3452929
Kind Code:
B2
Abstract:
PCT No. PCT/JP94/01479 Sec. 371 Date Oct. 25, 1995 Sec. 102(e) Date Oct. 25, 1995 PCT Filed Sep. 7, 1994 PCT Pub. No. WO95/09399 PCT Pub. Date Apr. 6, 1995Datapath elements 11 to 1N can exchange data respectively with local memories 21 to 2N through data buses 61 to 6N, so that parallel operations can be performed. The data bus 61, which is connected with one datapath element 11, can be connected with the other data buses 62 to 6N through an interconnection network 5, so that by activating one datapath element 11 only, data exchange can be made with all of the local memories 21 to 2N through the data buses 61 to 6N and the interconnection network 5. Thus, the multiple datapath elements can perform the parallel operations with being related with the multiple local memories: and a simple configuration is employed such that one datapath element can access to any one of the local memories.
More Like This:
| JPS60101642 | INPUT CONTROL CIRCUIT OF MICROCOMPUTER |
| JPH04299417 | TOGGLE OPERATING METHOD |
Inventors:
Yukihiko Okumura
Toshio Miki
Tomoyuki Ohya
Yoshinori Miki
Toshio Miki
Tomoyuki Ohya
Yoshinori Miki
Application Number:
JP51020495A
Publication Date:
October 06, 2003
Filing Date:
September 07, 1994
Export Citation:
Assignee:
NTT DoCoMo, Inc.
International Classes:
G06F9/32; G06F9/38; G06F15/173; G06F15/80; (IPC1-7): G06F15/80; G06F15/17
Domestic Patent References:
| JP4181362A | ||||
| JP3125252A | ||||
| JP6332649A | ||||
| JP51101427A | ||||
| JP60134957A | ||||
| JP5189585A | ||||
| JP4271452A | ||||
| JP495131A | ||||
| JP267446U |
Attorney, Agent or Firm:
川▲崎▼ 研二