Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
TERNARY OUTPUT CIRCUIT
Document Type and Number:
Japanese Patent JPH07114361
Kind Code:
A
Abstract:

PURPOSE: To provide a ternary output circuit capable of preventing reduction of the degree of integration by back gate control circuit.

CONSTITUTION: An output signal COM at a Vcc level is output from an output terminal To by turning on a transistor Tr11 whose source is connected to a Vcc and whose drain is connected to the output terminal To. An output signal COM of a Vss level is output from the output terminal To by turning on a transistor Tr12 whose drain is connected to the output terminal To and whose source is connected to a Vss. An output signal COM of a -Vcc level is outputted from the output terminal To by turning on a transistor Tr13 whose drain is connected to the output terminal To and whose source is connected to a -Vcc whose voltage is lower than the Vss level. The back gates of the transistors Tr12 and Tr13 are connected to the -Vcc.


Inventors:
NAKAMURA TAKAYOSHI
Application Number:
JP25868793A
Publication Date:
May 02, 1995
Filing Date:
October 15, 1993
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
FUJITSU LTD
FUJITSU VLSI LTD
International Classes:
G02F1/133; G09G3/36; H03K19/20; (IPC1-7): G09G3/36; G02F1/133; H03K19/20
Attorney, Agent or Firm:
Hironobu Onda