Title:
【発明の名称】光結合集積回路アレイ
Document Type and Number:
Japanese Patent JPS59501431
Kind Code:
A
Abstract:
Two-dimensional semiconductor chips are stacked to form a three-dimensional array in which coupling between chips is effected optically. This permits the use of smaller chips, with a corresponding higher yield, and serves to reduce the chip area required for interconnecting leads. It also reduces the internal interconnection path lengths which, at present, limit the speed of operation.
Inventors:
Copeland, Jiyoung Alexander
Miller, Stewart, Edward
Miller, Stewart, Edward
Application Number:
JP50264983A
Publication Date:
August 09, 1984
Filing Date:
July 22, 1983
Export Citation:
Assignee:
Western Electric Kampany, Incorporated
International Classes:
G02B6/43; H01L27/15; H01L31/12; H01L31/14; H04B10/00; H01L27/14; (IPC1-7): G02B5/174; G02B7/26; H01L27/14; H01L27/15; H01L31/14
Domestic Patent References:
| JPS566479A | 1981-01-23 |
Attorney, Agent or Firm:
Masao Okabe (2 outside)