Title:
【発明の名称】出力バッファ回路
Document Type and Number:
Japanese Patent JP2573320
Kind Code:
B2
Abstract:
An output buffer produces an output data at an output terminal (26). A first MOS transistor (18) charges the output terminal (26) toward a first supply potential when turned on. The source and drain of the first MOS transistor (18) are connected between the output terminal (26) and a first supply potential terminal. A second MOS transistor (25) discharges the output terminal (26) toward a second supply potential when turned on. The source and drain of the second MOS transistor (25) are connected between the output terminal (26) and a second supply potential terminal. A resistive element (28) charges the gate of the second MOS transistor (25) toward the first supply potential when turned on. The resistive element (28) is connected between the first supply potential terminal and the gate of the second MOS transistor (25). The resistance value of the resistive element (28) has nearly a constant value.
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Inventors:
Shigeru Kumagai
Hiroshi Iwahashi
Hiroto Nakai
Hiroshi Iwahashi
Hiroto Nakai
Application Number:
JP17232188A
Publication Date:
January 22, 1997
Filing Date:
July 11, 1988
Export Citation:
Assignee:
Toshiba Corporation
Toshiba Microelectronics Co., Ltd.
Toshiba Microelectronics Co., Ltd.
International Classes:
G11C7/10; H01L21/822; H01L27/06; H03K17/16; H01L27/04; H03K19/003; H03K19/017; H03K19/0175; H03K19/0185; H03K19/0948; (IPC1-7): H03K19/0948; H03K17/16; H03K19/0175
Domestic Patent References:
| JP63136823A | ||||
| JP635553A |
Attorney, Agent or Firm:
Takehiko Suzue (2 outside)