PURPOSE: To reduce the signal interference between bit lines, to prevent the reduction of an operating speed and to improve reliability by making an array structure in which bit lines to be connected with memory cells selected simultaneously with a word line are not adjacent each other.
CONSTITUTION: At the time of a readout, in a case that a word line 4a selecting memory cells whose Y0 addresses are '0' is selected, transfer MOS transistors Q1, Q2 and Q5, Q6 are turned on-states and storage information are readout on bit lines 8a, 8b and 10a, 10b from memory cells MC11 and MC13 respectively. At this time, a word line 4b is non-selective and transfer MOS transistors Q3, Q4 and Q7, Q8 are in off-states and bit lines 9a, 9b and 11a, 11b are held at a constant potential. By this method, in the case that memory cells whose Y0 addresses are '0' each other in memory cells adiacent in a column direction are selected, the signal interference is reduced by arranging memory cells whose Y0 addresses are '0' with every other interval across memory cells whose Y0 addresses are '1' in the column direction each other.
ISHIBASHI KOICHIRO
UEDA KIYOTSUGU
SASAKI KATSURO
TOYOSHIMA HIROSHI
KOMIYAJI KUNIHIRO
HITACHI VLSI ENG