Title:
【発明の名称】PWM回路
Document Type and Number:
Japanese Patent JP3326619
Kind Code:
B2
Abstract:
A pulse width modulation circuit apparatus comprises delay gates, delay circuits and an A/D converter. The delay gates are connected in cascade fashion and delay an input clock signal by the same delay time with each delay gate. The delay circuits are furnished interposingly between the delay gates and derive as their common output the delayed clock signal from the delay gates. Because the number of delay gates through which the input clock signal passes is proportional to the delay time acquired, these components constitute a delay circuit arrangement that offers high levels of linearity. With the delay circuit arrangement in use, any one of the delay circuits constituting part of that arrangement is supplied selectively with an operating current as per the digital output from the A/D converter. This provides a delayed clock signal whose delay time matches the level of the input analog signal. Thus there is generated a pulse signal whose pulse width corresponds to the period from the time the input clock signal is given until the delayed clock signal is acquired. This pulse signal has a pulse width of excellent linearity corresponding to the level of the input analog signal.
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Inventors:
Daisuke Murakami
Hideki Yoshida
Hideki Yoshida
Application Number:
JP2054092A
Publication Date:
September 24, 2002
Filing Date:
January 08, 1992
Export Citation:
Assignee:
ソニー株式会社
International Classes:
G06J1/00; H03K7/08; H03M1/82; (IPC1-7): H03K7/08
Domestic Patent References:
| JP472910A |
Attorney, Agent or Firm:
Kuninori Funabashi