Title:
GENERATING CIRCUIT OF REFERENCE POTENTIAL
Document Type and Number:
Japanese Patent JPS6037021
Kind Code:
A
Abstract:
PURPOSE:To attain the suitable application of a dynamic semiconductor memory circuit to a reference potential circuit by providing a supply circuit for current of a comparatively high voltage produced by the low power consumption characteristics obtained by a dynamic action and a boot-up action. CONSTITUTION:A reference potential Vref is lowered and a booted-up potential Vx is reduced less than the difference between the power supply voltage Vcc and the threshold voltage VTP of a p-channel transistor Q (shown by a round mark). Thus a transistor Q2 is kept on for a period T3 when a control signal phi3 is kept under a negative state. Then a current is supplied to a reference potential output line 10 from the Vcc via a transistor Q1 for a period T1 during which a control signal phi1 is kept negative. While the Q2 is kept off when the Vref is set at a high potential. Thus no current supply circuit is formed to the line 10. Therefore the current is supplied to the line 10 when the level of the Vref is lower than the voltage of the Vcc. Then the potential Vref having a high level corresponding to the rise of the voltage of the Vcc is delivered.
Inventors:
KUWABARA SUMIO
Application Number:
JP14537983A
Publication Date:
February 26, 1985
Filing Date:
August 09, 1983
Export Citation:
Assignee:
NIPPON ELECTRIC CO
International Classes:
G11C11/417; G05F3/16; G05F3/24; G11C11/407; H03F1/30; (IPC1-7): G11C11/34; H03F1/30
Attorney, Agent or Firm:
Uchihara Shin
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