PURPOSE: To decrease the source resistance of a hetero-junction field effect transistor by a method wherein a resistance reducing layer, doped with no impurity, is formed between a gate contact layer and the first conductive type high impurity concentration cap layer.
CONSTITUTION: A non-doped InAlAs buffer layer 102, a non-doped InGaAs channel layer 103, a non-doped InAlAs spacer layer 104, an n-type InAlAs doped layer 105, a non-doped InAlAs gate contact layer 106, a non-doped InGaAs resistance-reduced 107, and an n-type InGaAs layer 108 are successively formed on a semiconductive InP substrate 101 using an MBE method. A source electrode 110 and a drain electrode 111 are formed on a film-formed wafer, they are annealed, and after a gate electrode forming part has been recess-etched, a gate electrode 109 is formed. Then, the effect of scattering of impurities in the resistance-reduced layer and the scattering of lattice can be reduced, and the mobility of majority carrier can be enhanced.
TAGUCHI TAKASHI
UENO YOSHIKI
