PURPOSE: To obtain the titled device easily manufactured at high yield and low cost by providing a photosensor array composed of SIT.
CONSTITUTION: The surface of a high resistant Si substrate 21 at 50Ωcm or more is covered with an SiO2 film of about 1μm, an n+ layer 22 being formed by As diffusion from the back surface, and the film 20 being then removed. An n+ layer 25 is formed by As ion implantation from the side of the substrate 21, thus compensating the terminal part 23 of the previously formed layer 22 for diffusion sag and impurity concentration and then accurately controlling the thickness b of a channel region 24. Next, after crystal defects are annealed, the region is covered with an SiO2 film 26 about 1μm long, and with the film 26 as a mask a control gate region 26, a p+ type shielding gate 27, and a p+ drain 28 are formed by successive diffusion. Thereafter, when wiring is carried out by providing an electrode window, the image pickup element is completed. The n- channel layer can be formed with accurate uniformity by the use of the high resistant n- substrate and diffusion and ion implantation in such a manner, and then fine working at a high cost in SIT manufacture becomes unnecessitated, resulting in obtaining the titled device consisting of excellent SIT picture element cells at a low cost.
TAMAMUSHI NAOSHIGE
TANAKA AKIMASA
| JPS52104076A | 1977-09-01 | |||
| JPS58105672A | 1983-06-23 |