PURPOSE: To process the vector instructions, which are sent from scalar units different by architectures, by one vector unit by executing the vector instructions corresponding to plural architectures by the single vector unit.

CONSTITUTION: For example, a vector unit 2 is internally provided with a constitution control register where data indicating the architecture of each of scalar units 1 connected to the vector unit 2 is held. This data indicating the architectures is outputted from the constitution control register to, for example, an instruction conversion means 3. Vector instructions sent from scalar units 1 are converted to instruction forms, in which they can be processed in the vector unit 2, in accordance with this data by the instruction conversion circuit 3 and are executed by a vector instruction executing means 4. Consequently, vector instructions different by forms sent from scalar units different by architectures are processed by the single vector unit.