PURPOSE: To attain the encoding where at least one "0" or two "0s" exist between a "1" and the next "1" in a 5-bit data train obtained through the conversion, by referencing data within 2-bit before and after a 2-bit data.

CONSTITUTION: A data and a clock from terminals 2, 3 are inputted to a shift register and converted in parallel. A programmable logic array 4 performs the conversion of Q1=(-I3)+I3×(-I4)×(-5)×I6)× (-I7), Q2=I3×I4×I3×(-I4)× [I6+(-I5)+(-I6)], Q3=(-I3)×(-I4)+I3× (-I4)×(-I5)×I6+I1×(-I2)×(-I3)× I4, Q4=I3×I4+(-I3)×I4×(-I1)×(-I2)+I2, Q5=[I5+(-I5)×(-I6)]×[(-I4)+I1× (-I2)×(-I3)×I4]. A shift register 5 outputs a data to an FF6 in the clock being 5/2 times the original clock and a 5-bit data is obtained from a terminal 9. Thus, the ratio of the maximum magnetization inverting interval to minimum one is decreased as small as 1.5.