INSULATED GATE FIELD-EFFECT TRANSISTOR - MATSUSHITA ELECTRONICS CORP

Title:

INSULATED GATE FIELD-EFFECT TRANSISTOR

Document Type and Number:

Japanese Patent JPS598375

Kind Code:

A

Abstract:

PURPOSE: To reduce the channel resistance when the titled transistor is in ON state by a method wherein an oblong concavity, having the prescribed angle to the direction <100>, is formed and a surface (001) or (010) is used as a channel, thereby enabling to increase the mobility of electrons.

CONSTITUTION: An etching is performed on the silicon substrate, having a face (100) and a facet in the direction <100>, in such a manner that an oblong concavity P having the angle of 45° to the direction <110> can be formed. The above-mentioned silicon etching is performed vertical to the surface (100). At this time, the side face etched in rectangular parallelepiped are formed into the faces (001) and (010), which is equivalent to the surface (100). These two surfaces are used as a channel part.

Inventors:

UEDA DAISUKE
TAKAGI HIROMITSU

Application Number:

JP11730382A

Publication Date:

January 17, 1984

Filing Date:

July 05, 1982

Export Citation:

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Assignee:

MATSUSHITA ELECTRONICS CORP

International Classes:

H01L21/336; H01L29/04; H01L29/10; H01L29/417; H01L29/423; H01L29/78; (IPC1-7): H01L29/60

Attorney, Agent or Firm:

Akira Kobiji (2 outside)

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