Title:
【発明の名称】レジスタ回路
Document Type and Number:
Japanese Patent JP2518642
Kind Code:
B2
Abstract:
A register sub-circuit for a logic system is described which is capable of loading a logic signal from a bus, holding the state of the logic signal, and dumping the logic signal onto a precharged high capacitance bus. The circuit is master/slave in operation permitting the register to simultaneously dump the current contents of the register at the same time a new value is being loaded into the register. The circuit operates with a single phase clock. The circuit is easily integratable. The circuit comprises a storage sub-circuit and one or more dump sub-circuits. The circuit presents a low capacitance load to the dump control line.
Inventors:
HOORU AARU BOODENSUTABU
Application Number:
JP9273987A
Publication Date:
July 24, 1996
Filing Date:
April 15, 1987
Export Citation:
Assignee:
HEWLETT PACKARD CO
International Classes:
G11C11/409; G06F7/00; G11C7/10; H01L21/8242; H01L27/10; H01L27/108; (IPC1-7): G11C11/409; G06F7/00; H01L21/8242; H01L27/10; H01L27/108
Attorney, Agent or Firm:
Hideo Ueno