Title:
LATCH UP WITHSTANDING EVALUATNG METHOD
Document Type and Number:
Japanese Patent JPH0675002
Kind Code:
A
Abstract:
PURPOSE: To obtain a method for evaluating latch up withstanding of the internal circuit of IC.
CONSTITUTION: A chip 1 is irradiated, at an arbitrary point on the rear surface thereof, with infrared ray 15, i.e., a disturbance causing latch up, and generation of latch up is then evaluated. An actinometer 19 and a quantity of light regulator 20 are additionally provided in order to measure the withstanding of latch up quantitatively. This method allows quantitative evaluation of latch up withstanding at an arbitrary point on a chip.
Inventors:
UENAKA MARIKO
Application Number:
JP25419392A
Publication Date:
March 18, 1994
Filing Date:
August 28, 1992
Export Citation:
Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
H01L21/66; G01R31/26; (IPC1-7): G01R31/26; H01L21/66
Attorney, Agent or Firm:
Kenichi Hayase