Title:
GATE ARRAY SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS6047442
Kind Code:
A
Abstract:
PURPOSE:To reduce the number of power supply wirings while improving the interchangeability of fundamental cells constituting a gate array semiconducltor device by adjacently forming the fundamental cells, shaping wiring layers mutually connected along borderlines among these cells and connecting both end sections of the wiring layers to the first and second power supply wirings formed to the surface while being penetrated through an inter-layer insulating layer. CONSTITUTION:A first fundamental cell 11 and a second fundamental cell 12 constituting a gate array semiconductor device are formed adjacently, the whole surfaces of these cells are coated with a field insulating layer 16, openings are bored near a borderline 13 between the cells 11 and 12, and the cells 11 and 12 are connected by a wiring layer 14. The whole surface containing the wiring layer 14 is coated with an inter- layer insulating layer 22, through-holes 18 and 19 are each bored positioned at the end sections 15 and 16 of the wiring layer 14, and the end sections 15 and 16 of the wiring layer 14 are each connected to a first power supply wiring 20 and a second power supply wiring 21 formed on the surface of the insulating layer 22. Accordingly, the interchangeability of the fundamental cells positioned at power supply leading-out terminals is improved.
Inventors:
YOSHIDA TAKETO
Application Number:
JP15607183A
Publication Date:
March 14, 1985
Filing Date:
August 26, 1983
Export Citation:
Assignee:
NIPPON ELECTRIC CO
International Classes:
H01L21/822; H01L21/82; H01L27/04; H01L27/118; (IPC1-7): H01L27/04
Domestic Patent References:
| JPS5753984A | 1982-03-31 |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)