Title:
【発明の名称】半導体容量素子構造および製造方法
Document Type and Number:
Japanese Patent JP3060995
Kind Code:
B2
Abstract:
A capacitor with a high dielectric-constant dielectric and a thick lower electrode decreases the leakage current. The thick lower electrode is on an interlayer insulating layer. Typically, the interlayer insulating layer is formed on or over a semiconductor substrate. The lower electrode has a top face, a bottom face, and side faces. The bottom face of the lower electrode is adjacent to the interlayer insulating layer. An insulating cap or cover layer is on and contacts the top face of the lower electrode. The insulating cap or cover layer covers the top face of the lower electrode and uncovers the side faces of the lower electrode. A capacitor dielectric layer covers and contacts the side faces of the lower electrode and the insulating cap or cover layer. An upper electrode is on and contacts the capacitor dielectric layer. The capacitor dielectric layer is sandwiched by the upper and lower electrodes to thereby constitute a capacitor structure.
Inventors:
Hiroshi Yamaguchi
Application Number:
JP14038497A
Publication Date:
July 10, 2000
Filing Date:
May 29, 1997
Export Citation:
Assignee:
NEC
International Classes:
H01L27/04; H01L21/02; H01L21/822; H01L21/8242; H01L27/108; (IPC1-7): H01L27/108; H01L21/822; H01L21/8242; H01L27/04
Domestic Patent References:
| JP7193136A | ||||
| JP56975A | ||||
| JP9116115A | ||||
| JP964298A | ||||
| JP8222712A | ||||
| JP9270498A |
Attorney, Agent or Firm:
Nobuyuki Kaneda (2 others)