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Patent Searching and Data


Title:
【発明の名称】半導体メモリ
Document Type and Number:
Japanese Patent JP2583547
Kind Code:
B2
Abstract:
To reduce the number of wirings required between a plurality of memory blocks and a plurality of error correction circuits and thereby reduce the chip area occupied by a semiconductor memory, the present invention provides a semiconductor memory which comprises (1) a plurality of memory blocks (12) for storing information bits, (2) another memory block (13) for storing test bits, (3) a plurality of multiplexers (26) disposed at the respective output sections of the memory blocks (12), (4) a plurality of parity test circuits (27) each responding to bit information for a parity test which is generated from one output from the corresponding one of the multiplexers (26), (5) a syndrome bus (22) responding to both the respective outputs of the parity test circuits (26) and the output of the another memory block (13), and (6) a plurality of error correction circuits (21) each responding to both output data (28) generated from the other output of the corresponding one of the multiplexers (26) and a syndrome generated from the syndrome bus (22).

Inventors:
HORIGUCHI SHINJI
AOKI MASAKAZU
ITO KYOO
Application Number:
JP386588A
Publication Date:
February 19, 1997
Filing Date:
January 13, 1988
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
G11C11/413; G06F11/10; G11C11/401; G11C29/00; G11C29/42; (IPC1-7): G11C29/00; G11C11/401; G11C11/413
Domestic Patent References:
JP62119800A
JP623499A
Attorney, Agent or Firm:
Junnosuke Nakamura