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Title:
【発明の名称】半導体装置
Document Type and Number:
Japanese Patent JP3303002
Kind Code:
B2
Abstract:
A semiconductor device by which a circuit having the same functions as those of the conventional circuits is realized with a very small number of elements, and complex logical functions can be designed simply, and further, its layout is also possible. A semiconductor device made up of at least one neuron MOS transistor having a gate electrode provided in a potentially floating state in a portion for isolating a source and drain region via a first insulation film, and plural control electrodes which are capacitively coupled to the floating gate electrode via a second insulation film, is characterized in that the first signal is inputted to a first control gate elctrode of the first neuron MOS transistor, the first signal is inputted to a first inverter comprising one or more stages, and the output of the first inverter is inputted to a second control gate electrode which is one of the plural control gate electrodes other than the first control gate electrode.

Inventors:
Naoshi Shibata
Tadahiro Ohmi
Application Number:
JP50673892A
Publication Date:
July 15, 2002
Filing Date:
March 21, 1992
Export Citation:
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Assignee:
Naoshi Shibata
Tadahiro Ohmi
UCT Co., Ltd.
I&F Co., Ltd.
International Classes:
G06F7/49; G06F7/50; G06F7/501; G06N3/063; G11C11/56; G11C16/04; G11C27/00; H01L29/788; H03K19/0944; (IPC1-7): H01L21/8247; G06G7/60; H01L27/115; H01L29/788; H01L29/792
Domestic Patent References:
JP36679A
JP2264381A
JP61255070A
JP59175770A
JP4503270A
Other References:
【文献】米国特許5028810(US,A)
【文献】米国特許4999525(US,A)
【文献】米国特許4961002(US,A)
【文献】米国特許4950917(US,A)
Attorney, Agent or Firm:
Hisao Fukumori