Title:
【発明の名称】半導体集積回路装置
Document Type and Number:
Japanese Patent JP2625500
Kind Code:
B2
Abstract:
PURPOSE:To reduce a parasitic capacitance, to improve frequency characteristics, and to realize a rapid operation speed by reducing a corner section of a square of a buried operational region of a bi-polar transistor of vertical structure. CONSTITUTION:In a semiconductor integrated circuit device having a bi-polar transistor of vertical structure, which is provided with a buried n<+>-type semiconductor region 2 (a collector region) whose plane is formed in a square inside a semiconductor substrate 1, a corner section of the square of the buried n<+>-type semiconductor region 2 is reduced. Therefore, a periphery length of the buried n<+>-type semiconductor region 2 can be reduced, thus reducing a p-n junction area to the buried n<+>-type semiconductor region 2 and the semiconductor substrate 1 as well as a collector-to-substrate parasitic capacitance CTS. According to this constitution, frequency characteristics can be improved and a rapid operational speed can be realized.
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Inventors:
Hirotaka Nishizawa
Seiichiro Higashi
Kazuaki Ouri
Miyama Masataka
Shuji Kawada
Seiichiro Higashi
Kazuaki Ouri
Miyama Masataka
Shuji Kawada
Application Number:
JP13609788A
Publication Date:
July 02, 1997
Filing Date:
June 02, 1988
Export Citation:
Assignee:
株式会社日立製作所
日立超エル・エス・アイエンジニアリング株式会社
日立超エル・エス・アイエンジニアリング株式会社
International Classes:
H01L29/73; H01L21/331; H01L27/06; H01L29/72; H01L29/732; (IPC1-7): H01L21/331; H01L29/73
Domestic Patent References:
| JP6265370A | ||||
| JP1286464A |
Attorney, Agent or Firm:
Akita Aki