Title:
【発明の名称】半導体集積回路装置
Document Type and Number:
Japanese Patent JP3128262
Kind Code:
B2
Abstract:
In a CMOS-DRAM, an n-type silicon substrate has a p-type well formed therein, and a DRAM cell array is formed in the p-type well. In a period immediately after an external power supply is turned on, the p-type well is in a substantially floated condition. A predetermined time after the external power supply is turned on, the p-type well is applied with a predetermined DC voltage generated by a well voltage generating circuit. The CMOS-DRAM has a selective grounding circuit. When the external power supply is turned on, the selective grounding circuit forcibly grounds the plate electrode of the DRAM cell array for a predetermined period of time. Therefore, an increase in the well voltage at the cell array region, which increase may occur due to the capacitive coupling, is prevented when the power supply is turned on. Accordingly, adverse effects arising from the increase in the well voltage are prevented.
Inventors:
Takehiko Hara
Hideo Fujii
Hideo Fujii
Application Number:
JP12393691A
Publication Date:
January 29, 2001
Filing Date:
May 28, 1991
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
H01L27/08; G11C11/407; G11C11/4074; G11C11/408; H01L21/8242; H01L27/02; H01L27/10; H01L27/108; H01L27/105; (IPC1-7): H01L27/108; H01L21/8242; H01L27/08
Domestic Patent References:
| JP63311696A | ||||
| JP1138679A | ||||
| JP63255959A | ||||
| JP63308794A | ||||
| JP63228742A | ||||
| JP2309661A | ||||
| JP60136253A | ||||
| JP62143454A | ||||
| JP3112158A |
Attorney, Agent or Firm:
Takehiko Suzue