Title:
【発明の名称】半導体メモリ試験装置
Document Type and Number:
Japanese Patent JP3095088
Kind Code:
B2
Abstract:
PURPOSE:To easily change the testing timing of the title device at the time of retesting a defective memory cell. CONSTITUTION:The address of the defective memory cell of a memory 7 to be tested written in a fail memory 9 is set in an address register 11 and, at the time of retesting the defective memory cell, a coincidence detector 10 detects coincidence between the set address and address pattern A of a algorithmic pattern generator 4. On the other hand, the data for selecting timing set used for retesting the defective memory cell are set in a timing set selecting register 13. According to the output on/off of the detector 10, a multiplexer 12 selects the output of the register 13 or the output of a timing set selecting memory 3 and supplies the selected output to a timing generator 5. It is also possible to mask the detection of a prescribed address bit when the detector 10 makes coincidence detection on the pattern A by providing a coincidence detection masking device 14. The data designating the address bit to be masked are set in a mask register 15.
Inventors:
Toshimi Ohsawa
Application Number:
JP28903591A
Publication Date:
October 03, 2000
Filing Date:
November 06, 1991
Export Citation:
Assignee:
Advantest Corporation
International Classes:
G01R31/3183; G11C29/00; G11C29/56; G01R31/28; (IPC1-7): G01R31/28; G01R31/3183; G11C29/00
Domestic Patent References:
| JP5673364A | ||||
| JP4339399A |
Attorney, Agent or Firm:
Kusano Taku (1 person outside)