Title:
【発明の名称】半導体記憶装置
Document Type and Number:
Japanese Patent JP2712175
Kind Code:
B2
Abstract:
PURPOSE:To obtain a pseudo static RAM having no loss in an access time by commonly placing two sense systems in respective memory cells. CONSTITUTION:The memory cell can be connected to any adjacent bit line by two transistors. A word line system is divided into the two systems, the word line can be independently selected and raised, the respective half of the bit lines are used to have the two sense systems and the sense system of a folded bit line system can be attained. For instance, when the word line WL0 is selected by a row decoder #1, the respective memory cells are connected every other bit line by the selected word line, respective sense amplifiers are connected to respective bit line pairs divided at the center and every other sense amplifier is activated by the sense amplifier activating signals of the two systems. Thereby, the pseudo static RAM having no loss in the access time is obtained.
Inventors:
Hideto Hidaka
Application Number:
JP11120387A
Publication Date:
February 10, 1998
Filing Date:
May 06, 1987
Export Citation:
Assignee:
Mitsubishi Electric Corporation
International Classes:
G11C11/403; G11C11/34; G11C11/401; G11C11/405; H01L21/8242; H01L27/10; H01L27/108; (IPC1-7): G11C11/401; G11C11/403; G11C11/405; H01L21/8242; H01L27/108
Domestic Patent References:
| JP59129989A | ||||
| JP63222390A | ||||
| JP63234494A | ||||
| JP63275095A |
Attorney, Agent or Firm:
Fukami Hisaro (3 outside)