Title:
【発明の名称】半導体記憶装置
Document Type and Number:
Japanese Patent JP2772135
Kind Code:
B2
Abstract:
A semiconductor memory device comprises a memory cell array, a redundant memory cell array, bit line pairs, spare bit line pairs, a column address information storage circuit having stored therein information of a column address of a faulty cell and a column address of a spare cell, column decoders, a first column selecting gate for connecting one of the bit line pairs and first data output line pairs, a second column selecting gate for connecting one of the bit line pairs and a second data output line pair, a spare column decoder for selecting a third or a fourth column selecting line, a third column selecting gate for connecting the spare bit line pairs and the first data output line pairs, a fourth column selecting gate for connecting the spare bit line pairs and the second data output line pair, a first buffer for selecting two data and amplifying and outputting, a second buffer for amplifying and outputting data from the second data output line pair, and a register for storing therein data from the first and/or second buffers.
Inventors:
MAGOME KOICHI
SAWARA HIROSHI
TODA HARUKI
SAWARA HIROSHI
TODA HARUKI
Application Number:
JP30293290A
Publication Date:
July 02, 1998
Filing Date:
November 08, 1990
Export Citation:
Assignee:
TOSHIBA KK
International Classes:
G11C11/401; G11C11/407; G11C11/418; G11C29/00; G11C29/04; (IPC1-7): G11C11/401; G11C11/418; G11C29/00
Attorney, Agent or Firm:
Kazuo Sato (3 others)