Title:
【発明の名称】半導体記憶装置
Document Type and Number:
Japanese Patent JP2865712
Kind Code:
B2
Abstract:
PURPOSE:To attain the multifunction and high-performance of a memory device by dividing a memory array in the extending direction of a data line, and providing an arithmetic circuit which performs the prescribed arithmetic processing on the plural memory data read out from a column address corresponding to the each memory array adjacently to the extension line. CONSTITUTION:The memory arrays MARY0-MARY3 are divided in the extension direction of the data lines, and adjacently to the extension line, the operation circuits ALs which perform the prescribed operation processing on the plural memory data read out from the corresponding column address of the each memory array of MARY0-MARY3 are provided. And, for example, to the each memory array of MARY0-MARY3, the plural picture image data corresponding to the plural screens and the mask data, etc., previously to combine and partially delete these data are written in, simultaneously read out them and the various operation processings for the multidisplay of the screens and the image synthesis by window, etc., and the voice synthesis, etc., are performed. In such a manner, the data rate of the image processing system, etc., is restricted without disturbing the simplification, the multifunction and the high-performance are enhanced.
Inventors:
KOBAYASHI MITSUTERU
Application Number:
JP17790489A
Publication Date:
March 08, 1999
Filing Date:
July 12, 1989
Export Citation:
Assignee:
HITACHI SEISAKUSHO KK
International Classes:
G11C11/401; G06F12/00; G06F12/04; G06T1/60; G09G5/00; G09G5/12; G10L19/00; G10L25/00; G11C7/00; H01L27/10; (IPC1-7): G11C11/401; G06T1/60
Domestic Patent References:
| JP1143095A | ||||
| JP63204594A |
Attorney, Agent or Firm:
Katsuo Ogawa (1 person outside)