Title:
【発明の名称】半導体記憶装置
Document Type and Number:
Japanese Patent JP3099802
Kind Code:
B2
Abstract:
A layout of fuses for programming a redundancy circuit in a semiconductor device is provided, wherein the fuses are aligned to form at least one straight line which corresponds to at least one alignment of a plurality of bonding pads.
Inventors:
Mamoru Aoki
Application Number:
JP9784198A
Publication Date:
October 16, 2000
Filing Date:
April 09, 1998
Export Citation:
Assignee:
NEC
International Classes:
H01L27/10; G11C17/16; G11C29/00; H01L21/8242; H01L27/108; (IPC1-7): H01L27/108; H01L21/8242; H01L27/10
Domestic Patent References:
| JP61241943A | ||||
| JP5243387A |
Attorney, Agent or Firm:
Nobuo Takahashi (3 outside)