Title:
【発明の名称】半導体記憶装置
Document Type and Number:
Japanese Patent JP3365352
Kind Code:
B2
Abstract:
A semiconductor memory of the present invention includes a plurality of memory cell regions each being constituted by a particular memory cell and a plurality of word lines for selecting the memory cells. A word line driver circuit activates one word line to which a memory cell designated by the address signal is connected. A bit line connected to the memory cell selected by the activated word line reads data out of the memory cell. A sense amplifier amplifies a potential difference between two adjoining bit lines forming a bit line pair. A sense amplifier precharge circuit charges a power supply line and a ground line, which feed a voltage to the sense amplifier, to a preselected voltage. A driver circuit feeds to the gates of a first and a second n-channel MOS transistors in the sense amplifier precharge circuit a control signal of a preselected high level voltage from a third n-channel MOS transistor. The first and second n-channel MOS transistors feed a precharge current output from a precharge power supply to the power supply line and ground line, respectively. The sense amplifier precharge circuit may be replaced with or combined with an I/O line precharge circuit for precharging I/O lines.
Inventors:
Masamori Fujita
Application Number:
JP17900499A
Publication Date:
January 08, 2003
Filing Date:
June 24, 1999
Export Citation:
Assignee:
NEC
International Classes:
G11C11/409; G11C7/06; G11C7/10; G11C11/40; G11C11/401; H01L21/8242; H01L27/108; (IPC1-7): G11C11/409; G11C11/401; H01L21/8242; H01L27/108
Domestic Patent References:
| JP2146180A | ||||
| JP10134570A | ||||
| JP1154723A | ||||
| JP5712483A |
Attorney, Agent or Firm:
Nobuo Takahashi (3 outside)