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Patent Searching and Data


Title:
FABRICATION OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPH0774257
Kind Code:
A
Abstract:

PURPOSE: To increase the degree of freedom in the adjustment of wiring length by allotting more than one interface element for one pad, simulating the placement thereof, and connecting the input part commonly with one pad, thereby simplifying the routing through internal cells from the interface element and the adjustment of timing.

CONSTITUTION: In an LSI 100 under design, for example, three input buffers 14 are allotted to pas 11, two input buffers 15 are allotted to pad 12, and one input buffer 16 is allotted to pad 13. The input buffers 14-16 are placed between the pads 11-13 and a unit cell 17 and the pads 11-13 are connected with the input butters 14-16 which are then wired with the unit cell 17. Subsequently, the wiring between the input butters 14-16 and the unit cell 17 is adjusted based on the simulation. This method increases the degree of freedom in the adjustment of wiring between the input buffer and unit cell. Furthermore, the interval of pad can be set longer than that of the input buffer.


Inventors:
NOMURA KENICHI
UI NOBUYUKI
Application Number:
JP21780593A
Publication Date:
March 17, 1995
Filing Date:
September 01, 1993
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H01L21/82; (IPC1-7): H01L21/82
Attorney, Agent or Firm:
Keizo Okamoto