Title:
【発明の名称】シリアルデータの表示回路
Document Type and Number:
Japanese Patent JP2572734
Kind Code:
B2
Abstract:
PURPOSE:To display the initial bit of a serial data to the final stage of a display device at any time by adopting the 2nd clock sufficiently shorter than the 1st clock and counting the 2nd clock till the content reaches the setting value of the counter when the number of clocks is less than the setting value of the counter so as to drive a latch circuit. CONSTITUTION:In case of receiving a serial data 11, a counter 5 counts a clock 12 and in case of receiving a control signal 13, the control signal 13 switches a changeover device 4 and the counter 5 counts the clock 14. When the counter 5 counts '5', a latch circuit 7 drives it and in case of 3-bit serial data 11, when the control signal 13 enters, the clock 14 is fed to the input of the counter 5 so that the count of the counter 5 reaches '5' earlier. When the counter 5 counts '5', the initial bit of the serial data 11 is shifted up to the final stage of the shift register 6 and the state is displayed on a display device 8 as the output of the latch circuit 7.
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Inventors:
KAMO MASAHIKO
OORI KENJI
HARA KYOMI
OORI KENJI
HARA KYOMI
Application Number:
JP13500488A
Publication Date:
January 16, 1997
Filing Date:
June 01, 1988
Export Citation:
Assignee:
NIPPON DENSHIN DENWA KK
ANDO DENKI KK
ANDO DENKI KK
International Classes:
H04L1/24; H03M9/00; H04J3/14; H04L13/00; H04L69/40; (IPC1-7): H04L29/14; H03M9/00
Domestic Patent References:
| JP5983243A | ||||
| JP5851652A | ||||
| JP60178745A |
Attorney, Agent or Firm:
Masatake Shiga (2 outside)