Title:
HYBRID INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPS594132
Kind Code:
A
Abstract:
PURPOSE:To contrive high integration and miniaturization of the titled integrated circuit by a method wherein a frame member is provided around a semiconductor element, thereby enabling to mount a chip on both sides of a substrates. CONSTITUTION:A semiconductor element 4, a capacitor element 5 and the like are adhered to a substrate 1, and especially for said element 4, a connection by wire bonding and the like is performed. Then, the surface on the side of the elements 4 and 5 is positioned on the lower side. At this time, the damage on the semiconductor element 4 can be prevented by a frame 6 which is formed a little higher than the element 4 which is mounted on the substrate 1. Besides, as the heat conduction to be performed through the frame 6 can be done excellently, various types of connecting methods using a thermocompression bonding can be applied. Then, a connecting work is performed by adhering single-sided elements 4' and 5' on the above. Outside of the above is sheathed using protective resin and the like, and then epoxy or silicon or the like is applied. At this time, if a frame 6' is provided on the other single-side, protective effect and mechanical strength can be incrased still more. An insulating material such as resin and the like may be used for the frames 6 and 6'. A metal can be used, if the insulating means can be had for the wiring layer of the substrate and the mounted parts.
Inventors:
SENBA NAOHARU
Application Number:
JP11320582A
Publication Date:
January 10, 1984
Filing Date:
June 30, 1982
Export Citation:
Assignee:
NIPPON ELECTRIC CO
International Classes:
H05K1/18; H01L21/60; H05K3/34; (IPC1-7): H05K1/18
Attorney, Agent or Firm:
Uchihara Shin
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