PURPOSE: To operate securely counter circuits and to reduce the size and power consumption of a driving circuit, by operating two counter circuits in parallel and reducing counter clock frequencies to half.
CONSTITUTION: A counter circuit 11 counts (N-1)-bit value greater than an intermediate value among data of N-bit digital signals, and the other counter circuit 12 counts (N-1)-bit values less than the intermediate value. Then, two pulse- width modulated signals having pulse widths corresponding to the count times of the circuits 11 and 12 are led to a synthesizing circuit 5, whose output is sent to an integrating circuit 2'. Then, the circuit 2' obtains analog signals corresponding to said respective data of the digital signals, and they are amplified 3' to regenerate a sound through a speaker 4'.
OOGISHI TSUTOMU
KATOU SHINICHI
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