Title:
DIGITAL DEMODULATING CIRCUIT
Document Type and Number:
Japanese Patent JPS583403
Kind Code:
A
Abstract:
A digital circuit for demodulating a signal which was modulated in accordance with the relation wherein omega o is the carrier and f(t) the modulating signal. This circuit comprises first of all two distinct paths which are arranged in parallel and are formed by two digital value determining stages (20) and (30), the first stage being intended to determine the values of the function which correspond to the values of the input signal of the two paths and the second stage (30) being intended to determine the derivative of the input signal for said same values of the input signal. The circuit also comprises, at the output of these two paths, a multiplying circuit (40) for corresponding signals supplied by the first and second stages (20) and (30), intended to recover a digital signal which is proportional to the instantaneous frequency of the input signal. A clock circuit (50) determines the rate of operation of the first and second stages (20) and (30) and of the multiplying circuit (40).
Inventors:
JIERAARU RU FUROSHIE
Application Number:
JP10700182A
Publication Date:
January 10, 1983
Filing Date:
June 23, 1982
Export Citation:
Assignee:
PHILIPS NV
International Classes:
H03D3/00; H04N11/18; (IPC1-7): H03D3/00
Attorney, Agent or Firm:
Akihide Sugimura
Next Patent: TERMINAL MIGRATING SYSTEM