Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPS6028241
Kind Code:
A
Abstract:
PURPOSE:To form a wiring easily while obtaining the optimum arrangement by fitting terminals to the intermediate sections of a plurality of fundamental cell rows and input-output cells and bending and forming the wiring through said terminals when the fundamental cell rows are mounted to the central section of a semiconductor substrate and the input-output cells to the peripheral section of the substrate and the cell rows and the cells are connected mutually by using the wiring. CONSTITUTION:A plurality of fundamental cell rows 3 are respectively formed to the central section of a semiconductor substrate 1 while holding channel regions 4, input-output buffers 2 connected to the cell rows are fitted to the peripheral section of the substrate 1, and bonding pads 5 are connected to the cell rows and the buffers. The cell rows 3 and the buffers 2 are connected by lateral first layer Al wirings 8 crossing each channel region 4 and vertical second layer Al wirings 9, but a plurality of terminals 7 are formed previously among the cell rows and the buffers, and the cell rows and the buffers are each connected through the terminals. Accordingly, wiring inhibiting regions among the end sections of the cell rows 3 and the end sections of the buffers 2 are reduced, and the degree of freedom of the wirings is improved.
Inventors:
TAKECHI MAKOTO
Application Number:
JP13580883A
Publication Date:
February 13, 1985
Filing Date:
July 27, 1983
Export Citation:
Assignee:
HITACHI LTD
International Classes:
H01L21/822; H01L21/82; H01L23/528; H01L27/04; H01L27/118; (IPC1-7): H01L27/04
Attorney, Agent or Firm:
Akio Takahashi
Previous Patent: A manufacturing method of apparel products by which form stabilization was carried out, and apparel ...
Next Patent: JPS6028242
Next Patent: JPS6028242