Title:
INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPH0618628
Kind Code:
A
Abstract:
PURPOSE: To stop a boundary scanning test circuit, which is operated only at the time of the test in ordinary operation and to decrease power consumption by the amount in the ordinary operation.
CONSTITUTION: A boundary scanning test circuit comprises a boundary scanning register 5 contained in an I/O cell 3 around an integrated circuit chip 1 and a test control part 6, which is provided in an inner region 2. A test circuit 8 for an independent power source line is separately provided with respect to a main first power-supply line 7 for the boundary scanning test circuit. At the time of ordinary operation, a test-circuit power supply can be stopped, and the power consumotion can be decreased by that amount.
Inventors:
FUTATSUKA KAZUTSUGU
Application Number:
JP17223092A
Publication Date:
January 28, 1994
Filing Date:
June 30, 1992
Export Citation:
Assignee:
NEC CORP
International Classes:
G01R31/28; H01L21/822; H01L27/04; G01R31/26; (IPC1-7): G01R31/28; G01R31/26; H01L27/04
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)
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