PURPOSE: To prevent malfunction or abnormal operation by setting a discrimination output of a discrimination circuit and outputting a set output as a fault detection signal of a clock signal.

CONSTITUTION: A clock signal monitor circuit 15 is provided to monitor a clock signal of clock signal lines 11, 12, and when an error of the clock signal of any of the lines 11, 12 is detected, the error detection signal is inputted to a CPUA1 as an interrupt signal INT. When the CPUA1 receives the interrupt signal INT, the occurrence of a fault on a screen of a display device is displayed. That is, when the clock signal of a monitor object is unchanged over several periods, an output of each stage of a shift register goes all to a high level or a low level. Then flip-flop is set by a discrimination output from the discrimination circuit and the set output of the flip-flop is outputted as a fault detection signal of the clock signal.