Title:
【発明の名称】スタッフ分周回路
Document Type and Number:
Japanese Patent JPH088486
Kind Code:
B2
Abstract:
PURPOSE:To improve the reliability of a clock, by counting a 0-phase clock by an N-ary counter, delaying a generated ripple carrier by the 0-phase and a pi-phase clocks, and switching the 0-phase and the pi-phase clocks by the output signal of a delay part. CONSTITUTION:The 0-phase clock 1 and the pi-phase clock 2 oscillated by a master oscillator are inputted to the switching part 30 of a stuff frequency dividing circuit 20. Also, the 0-phase clock 1 is counted by the N-ary counter 21, and the generated ripple carrier 3 is inputted to the delay part 40, and it is delayed by the 0-phase clock 1 and the pi-phase clock 2. The output of the delay part 40 is inputted to the switching part 30 as a switching signal 7. A stuffed clock 6 that is a master clock is generated by switching the 0-phase clock 1 and the pi-phase clock 2, and an operation, for example, to reduce a difference between the minimum time and the maximum time of a cycle equivalent to the two cycles of the 0-phase clock is performed. In such a way, jitter generated by the unbalance of the time of the two cycles can be reduced, and the clock with high reliability can be generated.
Inventors:
Seiji Komatsuda
Application Number:
JP11982087A
Publication Date:
January 29, 1996
Filing Date:
May 15, 1987
Export Citation:
Assignee:
富士通株式会社
International Classes:
H03K5/156; H03K3/78; H03K5/00; H03K21/00; H03K23/64; (IPC1-7): H03K21/00; H03K3/78; H03K5/00; H03K5/156; H03K23/64
Attorney, Agent or Firm:
Teiichi
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