PURPOSE: To attain efficiency of a test in a way of enabling the test by provid ing a test circuit and separating a memory space control circuit and a CPU from the outside.
CONSTITUTION: A microcomputer is provided with a memory space control circuit, a test circuit and a CPU. When the memory space control circuit is tested at this stage, the result that the address signal inputted from an address bus ABUS is decoded by a decoder circuit DEC and the output signal of a register RG where the set range of memory space is stored are compared by gate circuits G1, G2, etc., and a data bus width control signal DBWC and an operation state number control signal STC to be outputted via buffers OB1, OB2 are outputted as a signal DBWC 1 and a STC 1, respectively, via the test circuit. Thus, a test can be performed by separating the only memory space control circuit.
JPH06208633 | PROCESSOR |
JPH0850573 | MICROCOMPUTER |
JPS5844558 | N-CHANNEL MOS SEMICONDUCTOR PROCESSOR |
HITACHI MICOM SYST KK