PURPOSE: To detect a potential defect in a decoder and an peripheral circuit by making plural pieces of columns and lines in a memory array into a non- selective state and finally applying a stress voltage when stress of the decoder and the peripheral circuit used together with a memory array is tested.

CONSTITUTION: First to fourth inverters 46, 48, 50, and 52 are directly connected between an address pad 54 and a first output signal line 56, and an output of the inverter 48 is connected to the input of a pass gate 58. The fifth inverter 60 is connected a between the output of the gate 58 and a second output signal line 62, and a signal Acomp therefrom and a signal ATRUE from the inverter 52 are inputted to an address decoder not shown in Figure. The inverters 46, 48, 50, and 52 are used for amplifying a driving performance to the signal ATRUE, and also generate a time delay to the signal ATRUE. Here, the time delay to Acomp is held equal to that of ATRUE, and the inverters 48 and 60 are made to use the gate 58 in order to optimize an intersection of these signals during a transition period.