PURPOSE: To furnish a shift register in which the number of controlling clocks is small and the arrangement is devised by precharging an output end by a clock- controlled transistor instead of raising the output end steadily by a load transistor.

CONSTITUTION: The high potential VGG of clock signals CL1, CL2, CL3 is selected above (VDD + threshold voltage of transistor), and an output of each step becomes a signal that swings fully between VDD and grounding potential. When the CL1 becomes VGG, a Tr11 becomes on, and the output end Q4 is raised to VDD. When the CL1 becomes grounding and CL2 becomes VGG, Tr11 is turned off and a Tr12 becomes on, and the potential of Q4 is determined according to gate potential of 13. At the same time, a Tr14 is turned on by the CL2 and an output end Q5 of the next step is raised to VDD. When the CL2 becomes grounding and the CL3 becomes VGG, the Trs 12, 14 are turned off and 15 is turned on. The Q4 is dynamically held at the previous potential and the Q5 becomes inverted potential. Consequently, data is shifted delayed by time t between rising edges of the CL3 and CL2.