Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
【発明の名称】スイツチト・コンデンサ・フイルタ
Document Type and Number:
Japanese Patent JPS59501729
Kind Code:
A
Abstract:
PCT No. PCT/GB83/00203 Sec. 371 Date May 7, 1984 Sec. 102(e) Date May 7, 1984 PCT Filed Aug. 12, 1983 PCT Pub. No. WO84/01065 PCT Pub. Date Mar. 15, 1984.A switched capacitor parasitic insensitive integrator comprises an operational amplifier (6), an integrating capacitor C2, a switched capacitor C, and four switches, two of even phase E1, E2 and two of odd phase 01, 02. In order to minimize the effect of capacitances (42) associated with the switches a 4-phase switching waveform is used such that E2 opens before E1, 02 opens before 01, E1 is not closed when 01 is closed and E2 is not closed when 02 is closed. A clock circuit may be used to provide the appropriate 4-phase switching waveform with a separate phase signal to each switch or a 2-phase switching waveform may be used with one phase signal to the E switches and the other phase signal to the O switches and the two switches E2, 02 biassed relative to E1, 01 such that the required differences in switching times occur.

Inventors:
Hague david jyoge
Sing Basian
Application Number:
JP50278383A
Publication Date:
October 11, 1984
Filing Date:
August 12, 1983
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
United Kingdom
International Classes:
G06G7/186; H03H19/00; (IPC1-7): G06G7/186; H03H19/00
Attorney, Agent or Firm:
Nobuhiko Nakajima



 
Previous Patent: JPS59501728

Next Patent: JPS59501730