Title:
【発明の名称】同期式直並列カウンタ回路
Document Type and Number:
Japanese Patent JP2544975
Kind Code:
B2
Abstract:
A synchronous programmable binary counter has a parallel section and a serial section, with the length (in bits) of the serial section being the same as the modulus of the parallel section. The parallel section counts on system clocks and produces two outputs. A parallel terminal count output is produced each time the parallel section count reaches a programmed value. A frame output is generated every time the parallel section reaches its maximum count and starts counting again. The serial counter section decrements its programmed value by one each time it receives a frame signal from the parallel section. This subtraction is accomplished by a half-adder and associated borrow flip-flop. The borrow flip-flop is set by each arrival of the frame signal. Between frame signals, the decremented programmed value is circulated in a shift register as the serial subtraction process is performed. When the serial section completes its countdown, it detects the all zeros condition in its circulating shift register and sets a flip-flop indicating that it has reached its terminal count. The overall counter will complete its count and will generate a terminal count output when the parallel counter section reaches its next terminal count. The maximum count possible from this counter is S * 2 S+S, where S is the length of the serial section and the maximum count of the parallel section.
Inventors:
DEBITSUDO EITSUCHI EBII
Application Number:
JP19378589A
Publication Date:
October 16, 1996
Filing Date:
July 26, 1989
Export Citation:
Assignee:
SONY TEKTRONIX CORP
International Classes:
H03K23/00; H03K23/50; H03K23/54; H03K23/66; (IPC1-7): H03K23/66; H03K23/00
Domestic Patent References:
| JP4864868A | ||||
| JP58129833A |