Title:
【発明の名称】テスト考慮論理合成システム
Document Type and Number:
Japanese Patent JP2865136
Kind Code:
B2
Abstract:
In a logic synthesis-for-testability system including a memory unit (101) for memorizing, as an objective circuit description which is logically synthesized, an FSM (finite state machine) description having a plurality of states, a testability improving unit (106) includes a candidate selecting unit (111) for selecting candidate states among the plurality of states with an asynchronous reset state of the plurality of states excluded from the candidate states. The testability improving unit improves a testability of the FSM description by reducing an average distance between all pairs of the plurality of states by selecting (112) a center state from the candidate states and providing (113) the FSM description with new transitions, each of which is directed to the center state from each of the plurality of states other than the center state. The candidate selecting unit may select the candidate states among the plurality of states with the asynchronous reset state and near states of the plurality of states excluded from the candidate states. Each of the near states has a distance which is calculated from the asynchronous reset state to each of the near states and which is shorter than a predetermined threshold value.
Inventors:
ASAKA TOSHIHARU
Application Number:
JP29840196A
Publication Date:
March 08, 1999
Filing Date:
November 11, 1996
Export Citation:
Assignee:
NIPPON DENKI KK
International Classes:
G06F11/22; G06F11/267; G01R31/28; G06F17/50; H01L21/82; (IPC1-7): G06F17/50
Attorney, Agent or Firm:
Yosuke Goto (1 person outside)