Title:
【発明の名称】薄膜メモリ
Document Type and Number:
Japanese Patent JP2979095
Kind Code:
B2
Abstract:
PURPOSE:To improve a degree of integration by surrounding the periphery of a semiconductor layer of a rectifying thin film diode with a memory insulating film having a charge trapping function. CONSTITUTION:The periphery of a semiconductor layer 14 of a rectifying thin film diode D is surrounded with a memory insulating film 16 having a charge trapping function. If a reverse bias voltage of a high voltage is applied to the diode D to implant electrons to the film 16 of the periphery of the semiconductor layer to write, the electrons trapped to the film 16 are trapped by the film 16. Since reading is performed by applying a forward bias voltage of a low voltage to the diode D, the area of its element is reduced to raise the degree of its integration.
Inventors:
YAMADA HIROYASU
Application Number:
JP2817190A
Publication Date:
November 15, 1999
Filing Date:
February 09, 1990
Export Citation:
Assignee:
KASHIO KEISANKI KK
International Classes:
H01L21/8247; H01L21/8229; H01L27/10; H01L27/102; H01L27/12; H01L29/788; H01L29/792; (IPC1-7): H01L27/10
Domestic Patent References:
| JP4839862U | ||||
| JP4839863U |