Title:
【発明の名称】薄膜トランジスタ
Document Type and Number:
Japanese Patent JP2982270
Kind Code:
B2
Abstract:
PURPOSE:To enable a leakage current of a TFT to be reduced without increasing the dimension of the TFT device, by providing an insulation film of the same pattern as a gate electrode of the TFT, under the gate electrode, and by providing an offset region between the gate electrode and a drain of the TFT, on the side face of the insulation film just under the gate electrode. CONSTITUTION:On a silicon substrate 1, a silicon oxide film 2 is formed, and after depositing a polysilicon film, a gate electrode 3 of a TFT is formed by patterning. Then, a gate insulation film 4 comprising a silicon oxide film is formed, and a polysilicon film 5 to come into a channel is formed, and further, by implanting ions thereinto, a source 6 and a drain 7 of the TFT are formed. At this time, owing to the thickness of the silicon oxide film 2, offsets 8 and 9 are formed between the gate electrode 3 and the source 6 of the TFT and between the gate electrode 3 and the drain 7 of the TFT respectively. Thereby, without increasing the area of a chip, the offset regions are formed in three dimensions, and it is made possible to integrate the TFT devices with a high density.
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Inventors:
OBARA SHINJI
Application Number:
JP26435590A
Publication Date:
November 22, 1999
Filing Date:
October 01, 1990
Export Citation:
Assignee:
NIPPON DENKI KK
International Classes:
H01L27/11; H01L21/336; H01L21/8244; H01L29/78; H01L29/786; (IPC1-7): H01L29/786; H01L21/336; H01L21/8244; H01L27/11
Domestic Patent References:
| JP1179367A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)