Title:
【発明の名称】ターンオン制御回路
Document Type and Number:
Japanese Patent JP3384834
Kind Code:
B2
Abstract:
A circuit (2) comprising a comparator (15) supplied with a turn-on voltage (VST) increasing gradually during the turn-on phase of a device (1) for protection. When the control voltage reaches a predetermined value (V1), the comparator (15) supplies a diagnostic enabling signal (Vo1) to a diagnostic stage (6, 8), which, in the event an undesired condition is detected at the output (7) of the device (1), supplies a clamp enabling signal to the control terminal of a clamping transistor (23) located between the input (19) of the circuit and ground, and which, when enabled, prevents the turn-on voltage (VST) from increasing further, and so prevents the device (1) from being turned on.
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Inventors:
Edoardo Botti
Andrea Fassina
Andrea Fassina
Application Number:
JP12935993A
Publication Date:
March 10, 2003
Filing Date:
May 31, 1993
Export Citation:
Assignee:
SGS-THOMSON MICROELECTRO NICS S.R.L.
International Classes:
H03F1/00; H02H7/20; H02H11/00; H03F1/30; H03F1/52; H03G3/30; (IPC1-7): H03F1/00; H03G3/30
Domestic Patent References:
| JP5327364A | ||||
| JP3159408A |
Attorney, Agent or Firm:
Soga Doteru (6 people outside)